FIG. 9 shows the representative schematic configuration of a semiconductor test apparatus. The main configuration elements include a timing generator TG, a pattern generator PG, a waveform formatter FC, a pin electronics PE, a performance board PB, a transmission line CB1, a logic comparator DC, and a fail memory FM. The pin electronics PE is provided with a driver DR or a comparator CP, etc. Here, since the semiconductor tester is publicly known and it is technically well known, the signals or configuration elements except the main elements related to this invention will not be described in detail.
FIG. 2 shows waveforms that indicate a driver terminal output pulse Vout to be outputted from an output terminal of the driver DR and a DUT terminal-applied pulse Vdut of an IC pin terminal of a DUT receiving the driver terminal output pulse Vout. Here, the DUT terminal-applied pulse Vdut is the pulse to be purposefully applied.
The high level component of the waveform to be supplied to the DUT decreases depending upon the transmission line CB1 coupled to the output terminal of the driver DR or the load of other elements. Accordingly, a circuit like a peaking circuit 4 shown in FIG. 1 for raising the high level component is mounted in the driver circuit. As the result of the peaking circuit, the waveform of the driver terminal output pulse Vout as shown by A and B of FIG. 2 is outputted. If this waveform reaches the IC pin of the DUT after transmitted through the performance board PB and the transmission line CB1, a proper waveform like the DUT terminal-applied pulse Vdut shown in FIG. 2, which is purposeful, can be applied.
FIG. 1 shows the principle configuration of a conventional driver circuit of an AE station type related to this invention.
The configuration elements of the driver circuit include a preceding stage and a last stage. The preceding stage is provided with transistors Q3 and Q4 which are differential switches, resisters R1 and R2, and a constant current source 2. Further, as a power source VL of the load coupled to the constant current source 2 a power source by which the circuit can operate is used. The last stage is provided with transistors Q1 and Q2 which are to be driven so that a predetermined waveform can be obtained in the DUT terminal, are sister R3, and a peaking circuit 4. The peaking circuit 4 is provided with a resistor 4 and a coil 4.
Here, the driver circuit of the AE station type is to regulate the amplitude of high and low levels to be a predetermined level by driving the last stage to perform current switching. Accordingly, its output terminal is configured with the NPN transistor and the resistor R3 of predetermined resistance. Further, the resistance of the resistor R3 is used about 50Ω in response to the impedance of the transmission line.
The preceding stage which is a differential amplifier receives a format signal DRP from the waveform formatter FC as a driver input pulse P1, converts it into a differential signal of predetermined amplitude by a predetermined voltage level, and supplies it to the base input terminal of the transistors Q3 and Q4, while supplying differential switch signals Q3s and Q4s inverted to have predetermined amplitude to the based input terminals of the corresponding last stage from the collectors of both the transistors.
The last stage which is a differential amplifier receives the differential switch signals Q3s and Q4s and outputs the driver terminal output pulse Vout buffered to predetermined drive capability by predetermined amplitude from the collector of the one-side transistor Q2. At this time, a high-side output voltage Vhi is determined by a power source voltage VH1, whereas a low-side output voltage Vlow is determined by {VH1−i1×R3}. Further, the waveforms of the rising and falling edges are outputted by the peaking circuit 4 in the form of the waveforms on which peaking compensation has been performed as shown by A and B in FIG. 2.
According to the conventional configuration as described above, it is necessary to use a coil device in order to realize the drive waveform on which peaking compensation has been performed. It is difficult to integrate the coil device into an LSI. Further, the peaking compensation processes for both rising and falling sides cannot be individually performed in the circuit configuration shown in FIG. 1. Accordingly, if the asymmetry of the waveform at the DUT terminal occurs, it is impossible to perform a symmetrical correction so as to obtain the desirable quality of the waveform. In addition, if the waveform to be applied to the DUT can be applied in a desirable state, the measurement quality of the device test by the semiconductor tester can be further improved.